1. Field of the Invention
The present invention relates to a digital control circuit of the proportional integral type.
Specifically, the invention relates to a digital control circuit of the P.I. (Proportional Integral) type, receiving an error signal at an input terminal and adapted to provide, at an output terminal, a PWM (Pulse Width Modulated) output signal, the circuit being of a type which comprises at least one analog-to-digital converter connected to said input terminal and to said output terminal through at least one integrative/proportional branch.
The invention relates, particularly but not exclusively, to a system for controlling a current in an inductive load, and this description covers this field of application for convenience of explanation only.
2. Description of the Related Art
As it is well known, there are a large number of applications where a current flowing through a load requires to be measured and controlled.
As an example, FIG. 1 shows schematically a conventional control system for controlling a current in an inductive load generally designated 10. In particular, the control system 10 includes an inductive load 11, which is connected between a first voltage reference, specifically a battery supply voltage VBAT, and an internal control node XC1 of the control system 10. A current IOUT1 flows through the inductive load 11 and requires to be measured. The control system 10 applies for this purpose a control of the PWM (Pulse Width Modulation) type, wherein only the feedback current of the load 11 is sensed by a first or sensing resistive element RS1 connected between the battery supply voltage reference VBAT and the control node XC1.
In particular, the first or sensing resistive element RS1 has a first terminal connected to said battery supply voltage reference VBAT and to a first input terminal of an error amplifier 12, and has a second terminal connected to said control node XC1, through a so-called free-wheeling diode DFW, and to a second supply voltage reference, specifically a ground voltage GND, through a series of a second or reference resistive element RF1 and a generator GREF1, generating a reference current IREF1.
The second or reference resistive element RF1 has a first terminal connected to the second terminal of the first or sensing resistive element RS1, and a second terminal connected to a second input terminal of the error amplifier 12. The error amplifier 12 also has an output terminal connected to a control circuit 13, in turn connected to a PWM drive element 14 that is connected between the control node XC1 and ground GND. In the embodiment of FIG. 1, the PWM drive element 14 comprises a MOS transistor.
The control system 10 uses said PWM drive element 14 to force the load current IOUT1 to a value that is proportional to the reference current IREF1 from the generator GREF1. In particular, when RF1=1000*RS1, it is:
IOUT1=1000*IREF1. 
FIG. 2 shows schematically a modification of the control system 10, which still applies a PWM type of control but involves measuring the whole load current.
In particular, FIG. 2 shows a control system 20, which includes an inductive load 21 connected between a first voltage reference, e.g. a battery supply voltage VBAT, through a first or sensing resistive element RS2, and a control node XC2. A current IOUT2 is circulated through the inductive load 21 whose full value is to be monitored and measured by means of the first or sensing resistive element RS2.
The first or sensing resistive element RS2 has a first terminal connected to said battery supply voltage reference VBAT, and to a second or supply voltage reference, specifically to ground GND, through a series of a second or reference resistive element RREF2 and a generator GREF2, generating a reference current IREF, and has a second terminal connected to said inductive load 21 and a first input terminal of an error amplifier 22.
Also, the interconnect point of the second or reference resistive element RREF2 and the generator GREF2 is connected to a second input terminal of the error amplifier 22.
The error amplifier 22 also has an output terminal connected to a control circuit 23, itself connected to a PWM drive element 24 that is connected between the control node XC2 and ground GND.
With the control system 20, and again when RREF2=1000*RS2, the value of the output current IOUT2 is tied to that of the reference current IREF2 as:
IOUT2=1000*IREF2. 
A further modification of the control system may be provided, which would still be based on a PWM type of control but use a measurement of the load voltage as shown schematically in FIG. 3.
In particular, FIG. 3 shows a control system 30 that includes an inductive load 31, connected between a control node XC3 and ground GND.
The control node XC3 is connected directly to a first input terminal of an error amplifier 32, which amplifier has a second input terminal connected to an internal voltage reference VREF3, and has an output terminal connected to a control circuit 33.
The control circuit 33 is in turn connected to the load 31 through a series of a PWM drive element 34 and an LC filter 35.
It should be noted that all of the prior applications shown schematically in FIGS. 1 to 3 employ a control circuit that is connected to a PWM load drive element to control a current of an inductive load.
Also known is to use control circuits operated by the P.I.D. (Proportional Integral Differential) method. These circuits are uniquely simple and effectual as concerns accuracy and speed of response.
FIG. 4 shows schematically a P.I. (Proportional Integral) type of control circuit 40, followed by PWM conversion (for compatibility), which circuit affords good control of a current circulated through an inductive load.
In particular, the control circuit 40 has an input terminal IN4 that is connected to a first or proportional block 42 and a second or integrator block 41, adapted for integration by a first coefficient Kp of proportionality and a second coefficient Ki of integration, in turn connected with their outputs to a summing node XS41.
The control circuit 40 includes a subtracting node XS42 connected (as positive addend) to the input of said summing node XS41 and (as negative addend) to an oscillator block 43, which block generates a ramp signal effective to cause said subtracting node XS42 to output a PWM signal.
The control circuit 40 further includes an output comparator 44, which is connected between said subtracting node XS42 and an output terminal OUT4 of the control circuit 40. In particular, the comparator 44 is a zero crossing type and outputs a logic high signal when the input is positive and a logic low signal when the input is negative.
FIG. 5 shows schematically waveforms of the most important variables in the PWM driven control circuit 40.
In particular, FIG. 5 shows a plot of a first output signal PI_output from said summing node XS41, taken to be constant for simplicity. This signal PI_output is compared with the signal generated by the oscillator block 43 at a frequency of 4 kHz.
The outcome of the comparison is a voltage signal Load Voltage for application to the load, also at a frequency of 4 kHz and with a duty cycle that will depend on the level of the signal PI_output with respect to the signal waveform. The signal Load Voltage is then filtered by the inductive load to emerge as a current signal Load Current that is substantially constant, as shown in FIG. 5 by way of example with an average level of 1 A and a ripple amplitude of 50 mA.
The control circuit 40 may be realized analogically, in a conventional manner as shown schematically in FIG. 6, where it is denoted generally by the reference numeral 60.
The analog embodiment 60 has an input terminal IN6 connected, through a first resistive element R61, to a first or inverting (xe2x88x92) input terminal of a first operational amplifier 61; the amplifier 61 also has a second or non-inverting (+) input terminal connected to ground GND, and has an output terminal connected, through a SampleandHold circuit 62, to a first or inverting (xe2x88x92) input terminal of a second comparator 63, which comparator has a second or non-inverting (+) input terminal connected to an oscillator 64, and has an output terminal connected to the output terminal OUT6 of the control circuit.
In particular, the second comparator 63 outputs a logic high signal when a signal is presented to the non-inverting input (+) which is higher in value than the signal to the inverting (xe2x88x92) terminal.
Moreover, by introducing the SampleandHold circuit 62, the comparator 43 is enabled to operate in the optimum conditions.
The analog embodiment 60 as shown further comprises a series of a second resistive element R62 and a capacitor C6, which are feedback connected between the output terminal and the first or inverting (xe2x88x92) input terminal of the operational amplifier 61.
This analog embodiment 60 of the control circuit 40 has some shortcomings originating essentially from that not all of its components can be integrated. For instance, the capacitor C6 is usually too large for integration. Also, changing the integration coefficients of the control circuit for adjustment of the control action to suit different working conditions is difficult.
From a simulation of the control system 20 shown in FIG. 2, and using an analog type of control circuit as shown in FIG. 6, it has been found that set point response does meet the speed and accuracy requisite of a final application that may be an ABS type of brake control system for an automobile vehicle (as shown schematically in FIG. 7).
The control circuit 40 may also be fully digitalized, as shown schematically at 80 in FIG. 8.
The digital embodiment 80 of the control circuit 40 has an input terminal IN8, which is input an analog error variable Error (an mA current signal); this signal is converted through an analog-to-digital converter 81 and sent, through a filter 82, to a first summing node XS81 and to a first proportional block 85 with a first coefficient of proportionality equal to 2xe2x88x927.
In particular, the analog-to-digital converter 81 is an 8-bit converter having a sampling frequency of 1 MHz and operative to convert the input error variable Error whose least significant bit represents a current of 5 mA.
Furthermore, the filter 82 calculates an average value over 250 xcexcs, with sampling at 4 kHz and holding for 250 xcexcs as shown schematically in FIG. 9A, where the FTR (Filter Time Response) of filter 82 for an output variable PWM Output of the PWM type provided by the digital embodiment 80 of a conventional control circuit, and a load current Load Current, are plotted against time. Shown schematically in FIG. 9B is a plot of the FFR (Filter Frequency Response) of filter 82, i.e. of the absolute value of a ratio sin(x)/x, where x is xcfx80f/4 kHz and f is the frequency.
Thus, a 16-bit word WORD is obtained at a rate of 4 kHz, with the filter 82 containing a DC component amplification factor 256.
The first summing node XS81 is also connected, through a 19-bit storage register 83 at 4 kHz having an output terminal feedback connected to said first summing node XS81, to a second or integrator block 84 that has a second coefficient Ki of integration 2xe2x88x9210.
These first or proportional and second or integrator blocks 85 and 84 are connected to a second summing node XS82 that outputs a 19-bit string WORD STREAM of words at 4 kHz, the string being sent to a subtracting node XS83 as a positive addend. The subtracting node XS83 also receives an output signal from an 8-bit counter 86, also known as the OVERFLOW COUNTER, as a negative addend.
In this way, only the most significant eight bit of the word string WORD STREAM are compared with the contents of the counter 86 to output a signal Output PWM at an output terminal OUT8.
FIG. 10 shows the result of a simulation of the control system 20 as shown in FIG. 2 providing a digital control as shown in FIG. 8. The simulated current set point response meets the speed and accuracy requirements.
While being advantageous on several counts, these prior solutions have a major drawback in that they are complicated in either the analog or the digital form.
The underlying technical problem of this invention is to provide a control circuit with structural and functional features adequate to overcome the limitations of prior circuits.
The principle on which this invention stands is one of having the analog-to-digital conversion and integration operations performed by a single element, so as to simplify the whole control circuit and improve its efficiency.
Based on this principle, the technical problem is solved by a circuit as previously indicated, and as defined in the characterizing part of claim 1.
The features and advantages of a control circuit according to the invention will be apparent from the following detailed description of embodiments thereof, given by way of non-limitative examples with reference to the accompanying drawings.